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STV7710
Vaccum fluorescent display (VFD) driver
Features

Figure 1.
Block diagram
CLK
96 outputs VFD driver 90 V absolute maximum supply 3.3V/5V compatible logic -40/30mA source/sink output MOS -50/50mA source/sink output diode 1-bit data bus (40 MHz) BCD process Packaging: die form
DATA_A
F/R
TEST
DATA_B 96bit Shift register
P1
P96
Latch
Description
STV7710 is a driver for vacuum fluorescent display (VFD) designed in the ST proprietary BCD high voltage technology. Using a 1 bit wide data bus, it can control 96 high current & high voltage outputs. The STV7710 is supplied with a separated 70V power output supply. All command inputs are CMOS and 3.3V logic levels compatible.
STB Q1 Q2 Q95 Q96
VSSLOG
VSSSUB POC & & & & VCC
BLK & & & &
STV7710
VSSP
OUT1
OUT96
VPP
July 2007
Rev 3
1/21
www.st.com
21
Contents
STV7710
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Die pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Mechanical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 3.2 Alignment marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pads specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 4.2 4.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 6 7 8 9 10 11 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input/ouput schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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STV7710
Block diagram
1
Figure 2.
Block diagram
STV7710 block diagram
CLK
F/R
TEST
DATA_A 96bit Shift register
DATA_B
P1
P96
Latch STB Q1 Q2 Q95 Q96
VSSLOG
VSSSUB POC & & & & VCC
BLK & & & &
STV7710
VSSP
OUT1
OUT96
VPP
3/21
Die pin assignment
STV7710
2
Die pin assignment
Figure 3. Die pin assignment
2.07
OUT54 OUT43
OUT55 OUT56 OUT57
OUT42 OUT41 OUT40
y
5.89
0/0
x
OUT95 OUT96 VPP VPP VSSP VSSP
OUT2 OUT1 VPP VPP VSSP VSSP
VSSLOG
4/21
VSSLOG
VSSSUB
TEST
POC
VCC
DATA_B DATA_A
CLK
BLK
STB
F/R
STV7710
Mechanical specification
3
3.1
Mechanical specification
Alignment marks
Figure 4. Alignment marks
min. 0.35 min 0.1 0.25
Patterning restricted area
min. 0.35
min 0.1
0.25
0.15
3.2
Pads specification
The reference is the centre of the die (x=0, y=0) Table 1. Top side from left to right
Centre: X -773.67 -670.48 -567.29 -464.1 -360.91 -257.72 -154.53 -51.34 51.85 155.04 258.23 361.42 Centre: Y 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 2796.11 Size: x 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 SIze: y 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
Name OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43
0.15
5/21
Mechanical specification Table 2. Bottom side from right to left
Centre: X 771.63 669.54 566.35 463.16 359.97 257.63 154.44 51.25 -119.85 -567.88 -669.54 -771.63 Centre: Y -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 -2802.23 Size: x 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
STV7710
Name VSSLOG CLK F/R POC VCC STB BLK DATA_A DATA_B VSSSUB TEST VSSLOG
SIze: y 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
Table 3.
Right side from top to bottom
Centre: X 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 Centre: Y 2050.11 1946.92 1843.73 1740.54 1638.88 1535.69 1432.50 1329.31 1226.12 1122.93 1019.74 916.55 813.36 710.17 606.98 503.79 400.60 297.41 194.22 91.03 Size: x 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 SIze: y 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
Name OUT42 OUT41 OUT40 OUT39 OUT38 OUT37 OUT36 OUT35 OUT34 OUT33 OUT32 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23
6/21
STV7710 Table 3. Right side from top to bottom (continued)
Centre: X 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 887.61 Centre: Y -12.15 -115.34 -218.53 -321.72 -424.91 -528.10 -631.29 -734.48 -837.67 -940.86 -1044.05 -1147.24 -1250.43 -1353.62 -1456.81 -1560.00 -1663.19 -1766.38 -1869.57 -1972.76 -2075.95 -2179.14 -2282.16 -2385.35 -2488.46 -2591.65
Mechanical specification
Name OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 VPP VPP VSSP VSSP
Size: x 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
SIze: y 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
7/21
Mechanical specification Table 4. Left side from bottom to top
Centre: X -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 Centre: Y -2591.65 -2488.46 -2385.35 -2282.16 -2179.14 -2075.95 -1972.76 -1869.57 -1766.38 -1663.19 -1560.00 -1456.81 -1353.62 -1250.43 -1147.24 -1044.05 -940.86 -837.67 -734.48 -631.29 -528.10 -424.91 -321.72 -218.53 -115.34 -12.15 91.03 194.22 297.41 400.60 503.79 606.98 710.17 813.36 916.55 Size: x 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
STV7710
Name VSSP VSSP VPP VPP OUT96 OUT95 OUT94 OUT93 OUT92 OUT91 OUT90 OUT89 OUT88 OUT87 OUT86 OUT85 OUT84 OUT83 OUT82 OUT81 OUT80 OUT79 OUT78 OUT77 OUT76 OUT75 OUT74 OUT73 OUT72 OUT71 OUT70 OUT69 OUT68 OUT67 OUT66
SIze: y 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
8/21
STV7710 Table 4. Left side from bottom to top (continued)
Centre: X -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 -887.61 Centre: Y 1019.74 1122.93 1226.12 1329.31 1432.50 1535.69 1638.88 1740.54 1843.73 1946.92 2050.11
Mechanical specification
Name OUT65 OUT64 OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55
Size: x 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00 92.00
SIze: y 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00 76.00
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Circuit description
STV7710
4
4.1
Circuit description
Pin description
Table 5.
Symbol OUT(01-96) VSSP VPP BLK POC F/R VCC VSSLOG VSSSUB CLK STB DATA_A DATA_B TEST
STV7710 pin description
Function Output Ground Supply Input Input Input Supply Ground Ground Input Input Input/output Input/output Input Power output Ground of power outputs High voltage supply of power outputs Blanking input Power output control input Selection of shift direction 5V logic supply Logic ground Substrate ground Clock of data shift register Latch of data to outputs Shift register input Shift register output Test input pin Description
4.2
Table 6.
F/R Input
Data bus configuration
STV7710 data bus configuration
Data shift Output CLK 01 02 02 95 03 03 94 04 04 93 05 05 92 06 06 91 ... 91 91 06 92 92 05 93 93 04 94 94 03 95 95 02 96 96 01 DATA_B DATA_A Forward shift Reverse shift
H L
DATA_A Output 01 DATA_B Output 96
This table describes the position of the first data sampled by the first rising edge of the CLK signal.
10/21
STV7710
Circuit description
4.3
Description
STV7710 includes all the logic and power circuits necessary to drive electrodes of a vacuum fluorescent display (VFD). Binary values of each pixel of the displayed line are loaded into the shift register DATA_A/B data bus. Data is shifted at each low to high transition of the CLK clock. After 96 shifts, the data is available at the output of the shift register. This output can be used to cascade several Ics to drive higher resolution displays. The forward /reverse (F/R) input is used to select the direction of the shift register. Data input/output status is set according to the selected direction (refer to Table 6). The maximum frequency of the shift clock is 40MHz. When the STB signal is high, data are transferred from the shift register to the latch and power output stages. All the output data are kept memorized and held in the latch stage when the latch input STB is set at low level. Vsssub and Vsslog must be connected as close as possible to the logical reference ground of the application. Also, make sure that TEST input pin is connected to ground (Figure 8). STV7710 is supplied with a 5 V power supply. All the logic inputs can be driven either by 5 V CMOS logic, or by 3.3 V CMOS logic. Table 7. Shift register truth table
Input F/R H H L L CLK H or L H or L Data-in / data-out Shift register function DATA_A Data-in Data-out DATA_B Data-out Data-in Forward shift Steady Reverse shift Steady
Table 8.
TEST L L L L L
Power output truth table
Qn X X X L H STB X X L H H BLK H L L L L POC X L H H H Driver output all "Low" all "High" Qn L H Comments Output at low level Output at high level Data latched Data transfered Data transfered
11/21
Absolute maximum ratings
STV7710
5
Absolute maximum ratings
Table 9.
Symbol VCC VPP VIN IPOUT Tjmax TSTG VOUT Logic supply range Driver supply range Logic input voltage range Driver output current(1) (2) Maximum junction temperature Storage temperature range Output power voltage range
Absolute maximum ratings
Parameter -0.3, +7 -0.3, +90 -0.3, Vcc+0.3 -40 / +30 125 -30, +150 -0.3, +90 Value V V V mA C C V Unit
1. Through one power output. 2. Through one power output for all power outputs (see Figure 6: Test configuration) with Junction temperature lower than or equal to Tjmax
ESD susceptibility - - Human Body Model: 100 pF; 1.5 k All pins withstand 2 kV except Data_A and Data_B: 1.2 kV
12/21
STV7710
Electrical characteristics
6
Electrical characteristics
(VCC = 5 V, Vpp = 70 V, VSSP = 0 V, Vss = 0 V, Tamb = 25 C, fCLK = 40 MHz, unless otherwise specified)
Table 10.
Symbol Supply VCC ICC ICCL ICC VPP IPPH Output
Electrical characteristics
Parameter Min Typ Max Unit
Logic supply voltage Logic supply current
(1)
4.50 MHz)(2) -
5 45 20 -
5.5 100 750 70
V A mA A V A
Logic dynamic supply current (fCLK=20 Logic supply current (VIH=2.0V) Power output supply voltage
15 -
Power output supply current (steady outputs)
10
OUT1-OUT96 (Figure 9) VPOUTH VPOUTL VDOUTH VDOUTL Power output high level (voltage drop versus VPP) @IPOUTH = - 20 mA and VPP = 70 V Power output low level @ IPOUTL = + 20 mA Output diode voltage drop @ IDOUTH = + 30 mA
(3)
-2
7.5 5 1 -1
14 11 2 -
V V V V
Output diode voltage drop @ IDOUTL = - 30 mA(3)
DATA A, DATA B (Figure 10) VOH VOL Input CLK, F/R, STB, POC, BLK, DATA_A, DATA B (Figure 8) VIH VIL IIH IIL CIN Input high level Input low level High level input current (VIH >=2.0V) Low level input current (VIL = 0v) Input capacitance(4) 2.0 0.9 5 5 15 V V A A pF Logic output high level @IOH=-1mA Logic output low level @IOL = 1 mA 4 4.8 0.1 0.4 V V
1. Logic input levels compatible with 5V CMOS logic. 2. All data inputs are commuted at 10MHz 3. See Figure 6: Test configuration 4. This parameter is measured during ST's internal qualification which includes temperature characterization on standard and corner batches of the process. This parameter is not tested on the part.
13/21
AC timing requirements
STV7710
7
AC timing requirements
VCC = 4.5 V to 5.5 V, Tamb = -20 C to +85 C, input signals max leading edge & trailing edge (tr, tf) = 5 ns.
Table 11.
Symbol tCLK tWHCLK tWLCLK tSDAT tHDAT tHSTB tSTB tSSTB
AC timing requirements
Parameter Data clock period Duration of CLK pulse at high level Duration of CLK pulse at low level Set-up time of data input before low to high clock transition Hold-time of data input after low to high clock transition Hold-time of STB after low to high clock transition Min 25 10 10 5 5 5 10 5 Typ Max Unit ns ns ns ns ns ns ns ns
STB low level pulse duration STB set-up time before CLK rise
14/21
STV7710
AC timing characteristics
8
AC timing characteristics
VCC = 5 V, VPP = 70 V, VSSP = 0 V, VSSSUB = 0 V, Vsslog = 0 V, Tamb = 25C, fCLK = 40 MHz (VILMAX = 0.2 Vcc, VIHMIN = 0.8 VCC)
Table 12.
Symbol tPHL1 tPLH1 tPHL2 tPLH2
AC timing characteristics
Parameter Delay of power output change after CLK transition - high to low - low to high Delay of power output change after STB transition - high to low - low to high Delay of power output change after BLK, POC transition - high to low - low to high Power output rise time(1) Power output fall time(1) Width of the falling edge smooth shape (not tested)(2) Logic data output rise time (CL = 10pF) Logic data output fall time (CL = 10pF) Delay of logic data output change after CLK transition - high to low - low to high Min Typ Max Unit
-
35 30 -
100 100 95 95
ns ns ns ns
-
tPHL3 tPLH3 tR OUT tF OUT tS tR DAT tF DAT tPHL4 tPLH4
50 50 -
25 20 30 9 5
90 90 200 200 20 12
ns ns ns ns ns ns ns
-
12 13
25 25
ns ns
1. One output among 96, loading capacitor CL = 50pF, other outputs at low level 2. See Figure 7: Zoom for OUTn showing tS and tF OUT
15/21
AC timing characteristics Figure 5. AC characteristics waveform
tCLK tWHCLK tWLCLK
STV7710
"1" CLK 50% 50% tSDAT 50% "0" tHDAT "1" DATA_A 50% tPHL4 tF DAT 50% "0"
DATA_B
tSTB
tPLH4
tHSTB
tR DAT "1"
STB 50%
50% "0" tSSTB
tPHL2 90% 10% tPLH2
tPHL1 "1" 90% 10% tPLH1 "0"
OUTn
"1" BLK
(POC="L")
50%
50% "0"
tPLH3 OUTn 10% 90%
tPHL3 90% 10% "1"
"0"
tF OUT
tR OUT
16/21
STV7710 Figure 6. Test configuration
VPP=VSSP
AC timing characteristics
VPP=VSSP
VDOUTH
IDOUTH
VDOUTL VSSP VSSP
IDOUTL
Output sinking current as positive value, sourcing current as negative value
Figure 7.
Zoom for OUTn showing tS and tF OUT
tF OUT OUTn 90%
10% tS
17/21
Input/ouput schematics
STV7710
9
Figure 8.
Input/ouput schematics
CLK, STB, F/R, POC, BLK inputs
VCC VCC
Figure 9.
Test pin
VCC
VCC
CLK, STB F/R, POC, BLK,
TEST
GNDSUB GNDSUB GNDLOG ! must be grounded in the application
GNDLOG
Figure 10. DATA_A, DATA_B
Figure 11. Power output
VCC VCC
VPP
DATA_A DATA_B
VCC
OUT1 to OUT 96
GNDLOG GNDSUB
VSSP
18/21
STV7710
Thermal characteristics
10
Thermal characteristics
STV7710 can be exposed to high temperatures during the manufacturing of the VFD module (display sealing). STV7710 is qualified for a maximum storage temperature of 475C during 30 minutes following the thermal profile described in Figure 12. Figure 12. Thermal profile applied for internal qualification
500
Temperature (C)
400 300 200 100 0 0 5 10 15 20 25 30 35 Time (minutes)
19/21
Ordering information
STV7710
11
Ordering information
Table 13. Order codes
Description Bare die Tested and usawn bump wafer (u=die) Unsawn wafer Dice on cavity plate (unit=die)
Part number STV7710 STV7710/BMP STV7710/WAF STV7710/WP
12
Revision history
Table 14.
Date 24-Mar-2004 30-Apr-2004 11-Jul-2007
Document revision history
Revision 1 2 3 Initial release. Renamed the document for STV7710/WAF order code. Added Chapter 11: Ordering information and Chapter 12: Revision history. Updated the document to cover all STV7710 order codes. Changes
20/21
STV7710
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